Power consumption caused by clock signals has always been a significant factor in a chip's overall power consumption. Naturally, as processor speeds continue to increase, power demands produced by those processors increase as well. Clock power, combined with a sequential element such as a flip flop can account for over sixty percent of a chip's power consumption. Thus, if the clock increases in frequency by twenty percent, a chip using the newer, faster frequency can consume, for example, approximately ten percent more power.
Many common flip flops are single edge triggered flip flops, and are triggered on the rising or falling edge of the clock signal. One example of a single edge flip flop is shown in FIG. 1.
The flip flop shown in FIG. 1 is triggered on the rising edge of the clock. When clk signal 101 is low, gate 109 is open and d 109 values can pass freely into the master node. The inversion of the clk signal at gate 105 makes a low clock value high, activating MOSFET transistor 109a. The twice inversion of the clk signal at gates 105, 107 and at MOSFET transistor 109b activates transistor 109b as well. When both transistors 109a and 109b are active, the signal d can pass through gate 109.
After passing through gate 109, the signal d is sent to a master gate 117 and to a feedback loop 115. The signal is twice inverted before reaching each destination. If the signal d is high, then MOSFET transistor 111a is not active, since there is an inverter which will drive the signal low. Consequently, no high signal from power source 112 can pass through gate 111 as feedback, regardless of the state of MOSFET transistor 111b. 
At the same time, MOSFET transistor 113b is active, so a low signal from ground 114 can pass through gate 113 as feedback if MOSFET transistor 113a is also active. When the clock is low, as in the present example, both transistors 111b and 113a are inactive.
Finally, during the clock low period, MOSFET transistors 117a and 117b are also inactive, closing gate 117 and preventing passthrough of the inverted d signal. The slave gate 119 is open, because MOSFET transistors 119a and 119b are both active, but the d signal is not being passed at this time and so the slave node retains its previous value. The slave value is also passed to q—1 after being inverted.
When the clk signal goes from low to high, several events occur. First, the gate 109 is closed, preventing passthrough of the d signal to the master node. Now the value of the master node is determined by the feedback loop 115, and is driven by the previous value of d. Since d was last passed as high, transistor 111a is still inactive, and transistor 113b is active. Transistors 111b and 113a are now also active, and the pairing of active transistors 113a and 113b opens gate 113 so that the low ground signal can pass through (which corresponds to the inverted high d signal previously being passed). Thus, the master node is storing the proper previously passed d signal, and changes to d cannot propagate to the master node.
In addition to closing gate 109, the changing of the clock from low to high opens gate 117, by activating transistors 117a and 117b. At the same time, gate 119 is closed and the signal stored by the master node feedback loop is passed to both q—1 (after being inverted once more).
Finally, when the clock toggles back from high to low, gate 109 is opened again, allowing new d signals to pass through, but gate 117 is closed, so the new d signal will not reach q—1 until the next rising edge. Slave node 121 is also now set with the previously passed d signal, since gate 119 is again opened.
Since the flip flop is triggered on the rising edge, the d signal can only pass through once per clock cycle. If flip flops could be triggered on both the rising and falling edge, however, then a frequency of ½ the standard frequency would produce similar power consumption and throughput results with a dual edge triggered flip flop as would a standard frequency in combination with a single edge triggered flip flop.
Dual edge triggered flip flops may, however, require more power consumption from the flip flop itself, to realize the dual edge triggering. Further, flip flops are often susceptible to “soft error.” Soft errors in chips can be caused by the presence of unwanted alpha particles or other unwanted energy resulting from material decay or cosmic rays (other causes of soft errors also exist). When such unwanted energy is present, it can disturb the electron distribution in the semiconductor, and, if present in large enough quantity, it can even flip a binary 0 to a 1 and vice-versa.
In the single edge flip flop shown, a soft error at just about any location during any clock cycle could cause an unknown state to occur. For example, if the error occurred in the master node during clock high, the master node value could be flipped and the wrong value could be passed as a result. If the soft error occurred in the slave node during clock low, again, the value 1 could be flipped and the wrong value could be stored by the slave. Since these nodes are driven by feedback, any soft error can disrupt the feedback and cause a change in value.
The illustrative embodiments provide dual edge triggered flip flops which are capable of lower power consumption, operation at lower clock frequencies with the same performance throughput as single edge flip flops at higher clock frequencies which can help reducing clock delivery power consumption as well, and/or which are soft error hardened to resist soft errors.
In one or more illustrative embodiments, the design of a dual edge triggered flip flop is such that the components themselves draw less power than a traditional single edge triggered flip flop, reducing power consumption of the flip flop itself.
In at least one illustrative embodiment, dual edge triggered flip flop further can be operated at approximately 50% clock frequency. Operating the flip flop at 50% clock frequency produces approximately the same performance as operating a single edge triggered flip flop at 100% clock frequency in conjunction with the same processor.
According to one or more illustrative embodiments, a dual edge triggered flip flop is also hardened against soft error. In at least one illustrative embodiment, a locking middle stage design provides such hardening. In this embodiment, when both master nodes have the same value which is true at roughly 90% time for microprocessor application, a soft error to one of two master nodes will cause the middle stage to lock and thus cause no change, and a soft error to the slave node may be driven out by the correct data in the master nodes. Thus the soft error rate will be reduced significantly.